The present invention relates to a novel composite controlled semiconductor device controlled by a voltage and a current and a power conversion device using such a semiconductor device, and more particularly to the structure of a composite controlled semiconductor device which is effective for the reduction of a loss in an ON state, the prevention of parasitic devices from operating and the reduction of an electric power for control.
Recently, IGBTs (or insulated gate bipolar transistors) have widely been used in place of GTOs (or gate turn-off thyristors) and MOSFETs (or power MOS transistors). The reason is that an ON/OFF control of the IGBT is easy as compared with that of the GTO since the IGBT is of a voltage controlled type and that an ON-state voltage of the IGBT is low as compared with that of the MOSFET since the IGBT is of a conductivity modulated type.
The IGBT includes, for example, a semiconductor body composed of an n layer epitaxially grown on a p.sup.+ substrate, an n layer formed on the n layer, a plurality of p layers regularly formed in the n.sup.- layer to expose an upper surface of the n.sup.- layer and an n.sup.+ layer provided in each p layer to expose an upper surface of the p layer, a collector electrode provided in ohmic contact with the p.sup.+ substrate, an emitter electrode provided in ohmic contact with the n.sup.+ layer and the p layer, and a gate electrode provided on an exposed surface of the n layer through an insulating film.
In the case where the IGBT having such a construction is used with the requirements in which a high withstand voltage is imposed, it is required that the n.sup.- layer be a relatively thick region in which a depletion layer dominantly extends. As the n.sup.- layer is made thicker, a significant problem arises in which conductivity modulation develops in an area of the n.sup.- layer near the p.sup.+ substrate which makes it more difficult for such modulation to take place in an area farther from the p.sup.+ substrate, thereby disabling the best use of the IGBT's feature of low ON-state voltage. A known scheme for solving this problem, is to provide a hole injecting p layer in an exposed surface of the n.sup.- layer on the emitter electrode side (see JP-A-3-23675).
The JP-A-3-23675 has disclosed a structure, as shown in FIG. 14, in which a p layer 214 is formed in a periphery portion of a semiconductor body and an electrode 223 in contact with the p layer 214 is connected to a gate electrode terminal G to supply a positive gate potential so that positive holes are injected from the p layer 214 into an n.sup.- layer 213. However, since the p layer 214 is provided in the periphery portion of the semiconductor body, positive holes injected from the p layer 214 scarcely reach a center portion of the semiconductor body of a several-millimeter square chip. That is, most of the positive holes are absorbed by a p layer 215 nearest to the p layer 214, thereby resulting in substantially no contribution to the reduction of an ON-state voltage. Especially, in a high-withstand voltage IGBT used at a voltage higher than 1000 V, a high conductivity modulation over the entire area is desired since the n.sup.- layer 213 becomes thicker than 100 microns.
Also, the IGBT shown in FIG. 14 has the following inconvenience. Namely, the gate electrode terminal G connected to the electrode 223 takes a voltage of about 15 V in an ON state. A potential relationship between a collector electrode 221 and an emitter electrode 222 of the IGBT in the ON state is such that the emitter electrode 222 takes a grounded potential and a low voltage of about 3 V is applied to the electrode 221. As the potential of the electrode 223 on the ON state becomes higher than that of the collector electrode 221, a pn junction between a p.sup.+ substrate 211 and an n layer 212 is reversely biased so that a large current flows from the p layer 214 into an n.sup.+ layer 216, thereby making a gate control difficult. In attempting to effect gate control of the IGBT, there arises a problem that a large electric power is required for the gate control.
Further, there is an inconvenience that a parasitic thyristor in a lateral direction including the p layer 214, the n.sup.- layer 213, the p layer 215 and the n.sup.+ layer 216 and a parasitic thyristor in a vertical direction including the p.sup.+ substrate 211, the n layer 212, the n.sup.- layer 213, the p layer 215 and the n.sup.+ layer 216 operate due to a large amount of positive holes injected from the p layer 214 and hence a control by an insulated gate including an insulating film 231 and an electrode 232 becomes difficult, thereby resulting in the breakage of the IGBT chip.
In addition, since a current density at the periphery portion of the semiconductor body is high and hence the amount of heat generated is large at the periphery portion, there is a problem that in the case where the collector electrode 221 is solder-secured to a heat sink which forms a part of a package, a strain stress of the periphery portion of the semiconductor body having the largest strain is further increased so that the IGBT chip is broken or becomes liable to peel off from the package even in the case where it is not broken.